This book presents the latest research results on the design of interconnect for programmable logic. The emphasis is on building the knowledge and tools for the automatic generation of interconnect structures. In this regard, the book presents design methodologies and applications for sparsely populated crossbars, clusters of lookup tables, switch blocks, and transistor-level routing switch design. It provides valuable information for both designers and architects about the area and delay implications of programmable interconnect. FPGA architects and System-on-Chip designers interested in exploring the integration of custom logic and programmable logic will find this work particularly useful.